Programming selective word lines during an erase operation in a memory device

A method, comprising:

• causing a first pulse to be to applied to a plurality of word lines coupled to respective memory cells in a memory array;
• causing a second pulse to be applied to a first set of word lines of the plurality of word lines;
• causing a third pulse to be applied to a second set of word lines of the plurality of word lines;
• and
• causing a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.

A memory device comprising:

• a memory array;
• and
• control logic, operatively coupled with the memory array, to perform operations comprising:
• receiving an erase command;
• executing an erase operation to erase a first set of word lines and programming a second set of word lines;
• and
• receiving an erase check command indicating to verify the erase operation responsive to executing the erase operation.