Memory system implementing write abort operation for reduced read latency

A memory system, comprising:

• a memory device comprising an array of storage transistors for storing data, the storage transistors being organized in a plurality of memory banks, each memory bank comprising a plurality of memory pages;
• and
• a controller device configured to interact with the memory device to perform read and write operations, each read or write operation being performed on a memory page in a memory bank,
• wherein the controller device is configured to issue to the memory device a write command and a write termination command, the write command causing the memory device to initiate a write operation in the memory device and the write termination command causing the memory device to terminate the memory operation, and wherein in response to a write operation being in progress at a first memory page in a first memory bank of the memory device and further in response to the controller device receiving a request for read data from a second memory page in the first memory bank, the controller device issues the write termination command to terminate the write operation in progress;
• and
• wherein each of the write operations comprises an erase phase followed by a program phase, each of the erase phase and the program phase comprises a set-up stage and a voltage pulse stage, and wherein in response to a first write command being issued to the memory device at a given memory page of a given memory bank to initiate a second write operation, the controller device tracks the phase of the second write operation being performed at the given memory page of the given memory bank of the memory device.

A method in a system in which a memory controller interacts with a memory device to perform read and write operations at the memory device, the memory device including storage transistors organized in a plurality of memory banks, each memory bank including a plurality of memory pages and each read or write operation being performed on a memory page in a memory bank, the method comprising:

• receiving, at the memory device, a first command being a write command and write data from the memory controller to perform a write operation at the memory device, the write command comprising at least a memory address specifying a first memory page of a first memory bank in the memory device at which the write data is to be stored;
• receiving, at the memory controller, a request for read data from a second memory page of the first memory bank;
• in response to receiving the request for read data for the first memory bank, determining, at the memory controller, the write operation associated with the first command at the first memory bank is in progress;
• in response to determining the write operation at the first memory bank is in progress, receiving, at the memory device, a second command from the memory controller to terminate the write operation in progress at the first memory bank of the memory device;
• and
• subsequent to terminating the write operation, receiving, at the memory device, a third command from the memory controller to read data from the second memory page of the first memory bank of the memory device, and
• wherein each of the write operations comprises an erase phase followed by a program phase, each of the erase phase and the program phase comprises a set-up stage and a voltage pulse stage, and the method further comprises, in response to a first write command being issued to the memory device from the memory controller at a given memory page of a given memory bank to initiate a second write operation, tracking at the memory controller the phase of the second write operation being performed at the given memory page of the given memory bank of the memory device.

A method in a memory device in which the memory device interacts with a memory controller to perform read and write operations at the memory device, the memory device including storage transistors organized in a plurality of memory banks, each memory bank including a plurality of memory pages and each read or write operation being performed on a memory page in a memory bank, the method comprising:

• receiving a first command being a write command and write data from the memory controller to perform a write operation at the memory device, the write command comprising at least a memory address specifying a first memory page of a first memory bank in the memory device at which the write data is to be stored;
• while the write operation is in progress at the first memory bank of the memory device, receiving a second command from the memory controller to terminate the write operation in progress at the first memory bank;
• and
• subsequent to terminating the write operation, receiving a third command from the memory controller to read data from a second memory page of the first memory bank of the memory device, and
• wherein each of the write operations comprises an erase phase followed by a program phase, each of the erase phase and the program phase comprises a set-up stage and a voltage pulse stage, and the method further comprises, in response to a first write command being issued to the memory device from the memory controller at a given memory page of a given memory bank to initiate a second write operation, tracking at the memory controller the phase of the second write operation being performed at the given memory page of the given memory bank of the memory device.

A method in a memory controller in which the memory controller interacts with a memory device to perform read and write operations at the memory device, the memory device including storage transistors organized in a plurality of memory banks, each memory bank including a plurality of memory pages and each read or write operation being performed on a memory page in a memory bank, the method comprising:

• issuing a first command being a write command with write data to the memory device to perform a write operation at the memory device, the write command comprising at least a memory address specifying a first memory page of a first memory bank in the memory device at which the write data is to be stored;
• receiving a request for read data from a second memory page of the first memory bank;
• determining the write operation associated with the first command at the first memory bank is in progress;
• issuing a second command to the memory device to terminate the write operation in progress at the first memory bank;
• and
• subsequent to terminating the write operation, issuing a third command to the memory device to read data from the second memory page of the first memory bank of the memory device, and
• wherein each of the write operations comprises an erase phase followed by a program phase, each of the erase phase and the program phase comprises a set-up stage and a voltage pulse stage, and the method further comprises, in response to a first write command being issued to the memory device from the memory controller at a given memory page of a given memory bank to initiate a second write operation, tracking at the memory controller the phase of the second write operation being performed at the given memory page of the given memory bank of the memory device.