Memory device using multistage acceleration, operating method of memory device, and electronic device including the same

A memory controller comprising:

• a register configured to receive instructions from a host;
• a decoder configured to decode the instructions;
• a command generator configured to generate a command to be provided to a memory package based on the decoded instructions, wherein the memory package comprises a plurality of memory devices;
• and
• a first accelerator circuit configured to receive second data from the memory package and perform first operations for an inference operation based on a neural network,
• wherein the second data is data obtained as a result of performing second operations on first data stored in the plurality of memory devices through a second accelerator circuit provided in the memory package, wherein the second operations comprise a filtering operation performed based on the first data.

An operating method of a memory controller connected to a memory package comprising a plurality of memory devices, the operating method comprising:

• receiving output data from a first accelerator circuit which has performed a coarse acceleration operation on sparse data stored in the plurality of memory devices to obtain the output data, wherein the coarse acceleration operation comprises a filtering operation performed based on the sparse data;
• obtaining an inference result by performing a fine acceleration operation on the output data by using a second accelerator circuit inside the memory controller;
• and
• providing the inference result to a host.