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US 12,631,677 B2Granted
Semiconductor device including separated electrode pads and method of manufacturing the same
AssigneeRenesas Electronics Corporation
InventorTakashi Tonegawa
Life of this patent
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Abstract
First conductive layer is connected to an impurity region which is a source region or an emitter region. A first conductive layer having an emitter pad and a second conductive layer having a Kelvin emitter pad and a relay pad are separated. A plane occupied area of the Kelvin emitter pad is smaller than a plane occupied area of the emitter pad.
Claims9
A semiconductor device, comprising:
- a semiconductor substrate having a main surface;
- a plurality of gate electrodes, each of the plurality of gate electrodes filling a trench;
- a plurality of impurity regions, each of the plurality of impurity regions being a source region or an emitter region and arranged in the semiconductor substrate;
- an interlayer dielectric layer arranged on the main surface;
- a first conductive layer connected to the plurality of impurity regions, arranged on the interlayer dielectric layer and having a first electrode pad;
- a second conductive layer arranged on the interlayer dielectric layer separately from the first conductive layer such that the plurality of gate electrodes and the plurality of impurity regions are not arranged in a region directly under the second conductive layer, the second conductive layer having a second electrode pad and a third electrode pad, the third electrode pad being electrically connected to the first electrode pad;
- and
- a dielectric layer arranged on the interlayer dielectric layer and located between the first conductive layer and the second conductive layer,
- wherein the first electrode pad is exposed from the dielectric layer,
- wherein the second electrode pad is exposed from the dielectric layer,
- wherein the third electrode pad is exposed from the dielectric layer,
- wherein a bonding wire connected to the second electrode pad,
- wherein a clip conductor arranged on the first electrode pad and the third electrode pad and electrically connected to each of the first electrode pad and the third electrode pad, and
- wherein a plane occupied area of the second electrode pad is smaller than a plane occupied area of the first electrode pad.
11 more elements
A method of manufacturing a semiconductor substrate, the method comprising:
- forming a plurality of gate electrodes in a semiconductor substrate such that each of the plurality of gate electrodes fills a trench;
- forming a plurality of impurity regions in a semiconductor substrate, each of the plurality of impurity regions being a source region or an emitter region;
- forming an interlayer dielectric layer on a main surface of the semiconductor substrate;
- forming a first conductive layer and a second conductive layer on the interlayer dielectric layer, the first conductive layer being connected to the plurality of impurity regions and the second conductive layer being separated from the first conductive layer, wherein the plurality of gate electrodes and the plurality of impurity regions are not arranged in a region directly under the second conductive layer;
- forming a dielectric layer on the interlayer dielectric layer, the dielectric layer exposing a first electrode pad of the first conductive layer, a second electrode pad of the second conductive layer and a third electrode pad of the second conductive layer;
- connecting a bonding wire with the second electrode pad;
- and
- connecting a clip conductor with each of the first electrode pad and the third electrode pad to electrically connect the first electrode pad with the third electrode pad,
- wherein a plane occupied area of the second electrode pad is smaller than a plane occupied area of the first electrode pad.
6 more elements
Dependencies are inferred from the claim text.