Over-voltage tolerant power supply sensing circuit with programmable trip-point

A method for sensing power comprising:

• sensing in a power sensing circuit in a first voltage domain an input voltage from a second voltage domain;
• protecting devices in the power sensing circuit in the first voltage domain from an overvoltage condition using a plurality of over-voltage protection devices;
• generating a high reference voltage, a mid-reference voltage, and a low reference voltage for use by the power sensing circuit;
• receiving the input voltage at a trip point device coupled between the input voltage and an internal trip point node;
• supplying a gate terminal of the trip point device with the low reference voltage;
• turning on the trip point device and passing the input voltage to the internal trip point node responsive to the input voltage becoming greater than a threshold voltage level;
• biasing an NMOS transistor coupled between the internal trip point node and a diode connected transistor using the mid-reference voltage;
• and
• supplying a power sense output node with a voltage sense output signal indicative of whether the input voltage is above the threshold voltage level.

A power sensing circuit in a first voltage domain to sense an input voltage from a second voltage domain, the power sensing circuit comprising:

• a power sense output node to supply a power sense output signal indicative of the input voltage;
• a voltage sense portion to sense the input voltage and generate an internal voltage sense signal on an internal voltage sense node indicative of the input voltage;
• a reference voltage generation circuit to generate a plurality of reference voltages including a high reference voltage, a mid-level voltage, and a programmable low reference voltage;
• an over-voltage tolerant Schmitt trigger circuit coupled between the internal voltage sense node and the power sense output node and coupled to receive the high reference voltage and the mid-level voltage as biasing voltages for respective protection transistors;
• a first stack of transistors coupled between the internal voltage sense node and a ground node, the first stack of transistors including a first protection device biased by the high reference voltage;
• a second stack of transistors coupled between the internal voltage sense node and the ground node, the second stack of transistors including a second protection device biased by the high reference voltage;
• a level shift circuit coupled between a gate terminal of one of the second stack of transistors and the power sense output node;
• and
• a trip point device in the voltage sense portion coupled to pass the input voltage when the input voltage is above a trip point, the trip point being determined, at least in part, according to a value of the programmable low reference voltage coupled to a gate terminal of the trip point device.