Isolated safety region of a system on a chip
AssigneeNVIDIA Corporation
InventorsPadam Patt Krishnani, Avinash J V, Shraddha Manohar Gondkar, Sowmya Satya Venkata Naga Siva Sai Bindu Mandapati
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AssigneeNVIDIA Corporation
InventorsPadam Patt Krishnani, Avinash J V, Shraddha Manohar Gondkar, Sowmya Satya Venkata Naga Siva Sai Bindu Mandapati
Estimating the term…
In various examples, an integrated circuit includes first and second portions. The first portion includes a timer that starts when the first portion transmits at least one error signal to the second portion. The timer may reset when data corresponding to at least one fault has been cleared from the first portion. The first portion transmits a timeout error signal when the timer indicates at least a predetermined amount of time has elapsed. The second portion receives the at least one error signal and the timeout error signal when the timeout error signal has been sent. The second portion may notify an external system after the timeout error signal is received.
A system on a chip (“SoC”) comprising:
A system comprising:
A method comprising:
Dependencies are inferred from the claim text.