Chip package with electromagnetic interference shielding layer and method of manufacturing the same

A method of manufacturing a chip package with at least one electromagnetic interference (EMI) shielding layer comprising the steps of:

• Step S1:
• providing a wafer on which a plurality of chips is disposed to form an array and each of the plurality of chips includes a surface on which at least one die pad and at least one chip protective layer are disposed;
• wherein a cut groove is formed between two adjacent chips of the wafer for separating the plurality of chips;
• Step S2:
• covering a surface of the at least one chip protective layer of the chip with a redistribution layer (RDL) and the RDL having at least one conductive circuit which is electrically connected with the at least one die pad of the chip while the at least one conductive circuit is provided with at least one pad which is exposed on a surface of the RDL for electrically connected with outside;
• Step S3:
• covering a surface of the RDL with an insulating layer completely and the insulating layer is provided with at least one first opening for allowing the at least one pad of the at least one conductive circuit to be exposed by the at least one first opening;
• Step S4:
• forming a peripheral wall around the at least one first opening of the insulating layer for enclosing the at least one first opening and forming a flat portion around the peripheral wall of the insulating layer;
• wherein a level of the flat portion is lower than a level of the peripheral wall;
• Step S5:
• covering the flat portion of the insulating layer with an electromagnetic interference (EMI) shielding layer and the EMI shielding layer is made of metal;
• wherein the EMI shielding layer is isolated and electrically insulated from the at least one pad by the peripheral wall of the insulating layer;
• and
• Step S6:
• cutting along the cut groove of the wafer for separating the plurality of chips on the wafer to form a plurality of chip packages.