Buried via-to-backside power rail (VBPR) for stacked field-effect transistor (FET)

A method of forming a semiconductor structure, the method comprising:

• forming a first field-effect transistor (FET) having a first source/drain;
• forming a second FET having a second source/drain, wherein the second FET is stacked above the first FET;
• forming a trench extending from above the second source/drain to beneath the first source/drain, wherein the trench passes (i) completely through the first source/drain, such that a sidewall of the trench includes a fully surrounding portion of a sidewall of the first source/drain, and (ii) through portions of the second source/drain;
• forming a bottom contact in the trench;
• forming a dielectric layer in the trench, the dielectric layer on a top surface of the bottom contact;
• and
• forming a top contact in the trench, the top contact on a top surface of the dielectric layer, wherein the dielectric layer (i) separates the top contact from the bottom contact and (ii) physically contacts both the top contact and the bottom contact along a plane parallel to the sidewall of the first source/drain.