Method of forming confined growth S/D contact defined by sidewall constraints with selective deposition of inner spacer for CFET

A method of manufacturing a semiconductor device, the method comprising:

• forming a stack of epitaxially grown layers alternating between a first semiconductor material and a second semiconductor material that is etch selective to the first semiconductor material;
• forming fin structures from the stack, the fin structures including channel structures formed of the first semiconductor material, the channel structures having opposing ends that are uncovered;
• forming sidewall constraints at the opposing ends of the channel structures, each pair of the sidewall constraints laterally bounding a respective source/drain (S/D) region at a respective end of the channel structures while having a respective top opening for accessing the respective S/D region;
• and
• forming S/D structures on the opposing ends of the channel structures by epitaxially growing a third semiconductor material between each pair of the sidewall constraints,
• wherein the third semiconductor material is epitaxially grown to a height below a top of the sidewall constraints.

A method of manufacturing a semiconductor device, the method comprising:

• forming a stack of epitaxially grown lavers alternating between a first semiconductor material and a second semiconductor material that is etch selective to the first semiconductor material;
• forming fin structures from the stack, the fin structures including channel structures formed of the first semiconductor material, the channel structures having opposing ends that are uncovered;
• forming sidewall constraints at the opposing ends of the channel structures, each pair of the sidewall constraints laterally bounding a respective source/drain (S/D) region at a respective end of the channel structures while having a respective top opening for accessing the respective S/D region;
• forming S/D structures on the opposing ends of the channel structures by epitaxially growing a third semiconductor material between each pair of the sidewall constraints;
• bonding a first wafer to a second wafer via a first bonding dielectric layer, the first wafer including a first bulk semiconductor material, the second wafer including the stack formed over a second bulk semiconductor material;
• and
• removing the second bulk semiconductor material to uncover the stack before forming the fin structures from the stack.