Insulated gate bipolar transistor (IGBT) semiconductor device with reduced turn-on loss

A semiconductor device, comprising:

• a first electrode;
• a second electrode;
• a semiconductor part located between the first electrode and the second electrode, the semiconductor part including
• a first semiconductor layer of a first conductivity type,
• a second semiconductor layer of a second conductivity type,
• a third semiconductor layer of the first conductivity type,
• a fourth semiconductor layer of the second conductivity type, and
• a fifth semiconductor layer of the second conductivity type;
• a group of gate electrodes located between the semiconductor part and the first electrode, the group of gate electrodes including one or more first gate electrodes, one or more second gate electrodes, and one or more third gate electrodes, each of the first to third gate electrodes in the group facing the first to third semiconductor layers and the first to third gate electrodes in the group being electrically isolated from each other;
• a first insulating film located between each of the one or more first gate electrodes and the semiconductor part;
• a second insulating film located between each of the one or more second gate electrodes and the semiconductor part;
• and
• a third insulating film located between each of the one or more third gate electrodes and the semiconductor part,
• the second semiconductor layer being located between the first semiconductor layer and the third semiconductor layer,
• the third semiconductor layer being located between the second semiconductor layer and the first electrode and electrically connected to the first electrode,
• the fourth semiconductor layer being located between the first semiconductor layer and the second electrode and electrically connected to the second electrode,
• the fifth semiconductor layer being located between the second semiconductor layer and the first electrode and electrically connected to the first electrode, the fifth semiconductor layer having a higher second-conductivity-type impurity concentration than the second semiconductor layer,
• the third semiconductor layer and the fifth semiconductor layer being alternately arranged in a direction in which the first to third gate electrodes extend,
• S1≤S2<S3 being satisfied, where S1 is a total surface area of the one or more first gate electrodes and the third semiconductor layer facing each other via the first insulating film, S2 is a total surface area of the one or more second gate electrodes and the third semiconductor layer facing each other via the second insulating film, and S3 is a total surface area of the one or more third gate electrodes and the third semiconductor layer facing each other via the third insulating film.