Memory device and method of manufacturing memory device

A memory device comprising:

• a substrate;
• a first bit line provided above the substrate;
• a first transistor including:
• a first semiconductor layer provided between the substrate and the first bit line;
• a first gate electrode facing a side surface of the first semiconductor layer;
• and
• a first gate insulating layer provided between the first semiconductor layer and the first gate electrode;
• a first memory element provided between the first transistor and the substrate;
• a first word line including a first conductive layer coupled to the first gate electrode;
• a second transistor including:
• a second semiconductor layer provided between the substrate and the first bit line;
• a second gate electrode facing a side surface of the second semiconductor layer;
• and
• a second gate insulating layer provided between the second semiconductor layer and the second gate electrode;
• a second memory element provided between the second transistor and the substrate;
• a second word line that is adjacent to the first word line in a first direction in parallel to a surface of the substrate and that includes a second conductive layer coupled to the second gate electrode;
• a second bit line provided above the substrate;
• a third transistor including:
• a third semiconductor layer provided between the substrate and the second bit line;
• a third gate electrode facing a side surface of the third semiconductor layer;
• and
• a third gate insulating layer provided between the third semiconductor layer and the third gate electrode;
• and
• a third memory element provided between the third transistor and the substrate, wherein
• the second semiconductor layer is adjacent to the first semiconductor layer in a second direction that is in parallel to the surface of the substrate and intersects the first direction, and
• the second transistor is provided at a position different from a position of the first transistor and a position of the third transistor in the first direction and is provided between the first transistor and the third transistor in a third direction that is in parallel to the surface of the substrate, intersects the first and second directions, and the first word line extends in the third direction.