Memory devices having vertical transistors and methods for forming the same

A method for forming an array of memory cells, comprising:

• forming a plurality of grooves having a second width, each groove extending laterally along a first lateral direction and vertically in an upper portion of a semiconductor layer;
• forming a sacrificial layer in each groove;
• forming a cap layer to alternatively cover the sacrificial layer in a first subset of grooves having a first parity;
• removing the sacrificial layer in a second subset of grooves having a second parity that are uncovered by the cap layer, and enlarging each of the second subset of grooves to from a plurality of first trenches each having a first width greater than the second width;
• depositing at least one dielectric material to form a bottom dielectric structure located in a lower portion of each first trench;
• oxidizing portions of the semiconductor layer to form gate dielectric layers on sidewalls of each first trench;
• and
• forming two disconnected conductive structures in each first trench, the disconnected conductive structures laterally extending in parallel along the first lateral direction.

A method for forming a semiconductor structure, comprising:

• during forming a plurality of first trenches having a first width forming a plurality of grooves having a second width less than the first width, each of the plurality of first trenches and the plurality of grooves extending laterally along a first lateral direction and vertically in an upper portion of a semiconductor layer, the plurality of first trenches and the plurality of grooves being alternatively arranged along a second lateral direction different from the first lateral direction;
• forming a spacer in each groove, wherein the spacer is laterally extending along the first lateral direction;
• depositing at least one dielectric material to form a bottom dielectric structure located in a lower portion of each first trench;
• oxidizing portions of the semiconductor layer to form gate dielectric layers on sidewalls of each first trench;
• and
• forming two disconnected conductive structures in each first trench, the disconnected conductive structures laterally extending in parallel along the first lateral direction.