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US 12,628,327 B2Granted
SRAM device for FPGA application
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsDian-Sheng Yu, Chun-Wei Chang, Jhon Jhy Liaw
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Abstract
A device includes a first transistor including a first drain/source terminal and a second transistor including a first gate terminal. A first conductive path is electrically connected between the first drain/source terminal and the first gate terminal. The first conductive path includes a first conductive via electrically connected between the first drain/source terminal and a first track of a first conductive layer, and a second conductive via electrically connected between the first track of the first conductive layer and a first track of a second conductive layer.
Claims20
A memory device, comprising:
- first and second transistors of opposite conductivity types, the first and second transistors sharing a first gate terminal, the first transistor including a first drain/source terminal, the first gate terminal extending longitudinally along a first direction;
- third and fourth transistors of opposite conductivity types, the third and fourth transistors sharing a second gate terminal, the third transistor including a second source/drain terminal, the second gate terminal extending longitudinally along the first direction;
- and
- a first conductive path electrically connected between the first drain/source terminal and the second gate terminal,
- wherein an extension of a centerline of the first gate terminal along the first direction intersects an edge of the second gate terminal, and
- wherein the first conductive path includes:
- a first conductive via electrically connected between the first drain/source terminal and a first track of a first conductive layer;
- and
- a second conductive via electrically connected between the first track of the first conductive layer and a first track of a second conductive layer positioned above the first conductive layer.
6 more elements
A memory device, comprising:
- a static random-access memory (SRAM) cell including:
- a first transistor including a first gate terminal and a drain/source terminal, the first gate terminal extending lengthwise along a first direction;
- a second transistor including a second gate terminal, the second gate terminal extending lengthwise along the first direction;
- a conductive path electrically connected between the drain/source terminal and the second gate terminal, the conductive path including:
- a first conductive via electrically connected between the drain/source terminal and a first track of a first conductive layer;
- a second conductive via electrically connected between the first track of the first conductive layer and a track of a second conductive layer;
- a third conductive via electrically connected between the second gate terminal and a first track of a third conductive layer;
- and
- a fourth conductive via electrically connected between the first track of the third conductive layer and the track of the second conductive layer,
- wherein the first transistor is a pull-down (PD) transistor of the SRAM cell and the second transistor is a pull-up (PU) transistor of the SRAM cell,
- wherein an extension of a centerline of the first gate terminal along the first direction intersects an edge of the second gate terminal, and
- wherein at least one of a second track of the first conductive layer and a second track of the third conductive layer align with at least one of a power rail and a reference rail.
9 more elements
A method for forming a memory device, comprising:
- providing, in a static random-access memory (SRAM) cell, a first transistor including a first gate terminal and a first drain/source terminal and a second transistor including a second gate terminal, each of the first and second gate terminals extending longitudinally along a first direction, each of the first and second transistors disposed on a straight line extending along the first direction, an extension of a centerline of the first gate terminal along the first direction intersecting an edge of the second gate terminal, wherein the first transistor is a pull-down (PD) transistor of the SRAM cell and the second transistor is a pull-up (PU) transistor of the SRAM cell;
- connecting, in a first conductive path, a first conductive via between the first drain/source terminal and a first track of a first conductive layer;
- and
- connecting a second conductive via between the first track of the first conductive layer and a track of a second conductive layer.
1 more element
Dependencies are inferred from the claim text.