System and design method of an ethernet controller of a combined centralized and distributed unit
AssigneeJio Platforms Limited
InventorsNarender Kumar, Shakti Singh, Amrish Bansal, Brijesh Shah, Bajinder Pal Singh, Selvakumar Ganesan
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Abstract
The present invention provides an efficient hardware architecture of an Ethernet controller to provide for connectivity interfaces to a combined centralized unit and a distributed unit (CCDU) for processing Level 1, 2 and 3 scheduling in a network. The CCDU design may provide the functionality of a CU and a DU as a single unit and the design of the Ethernet controller along with an eASIC comprising an accelerator unit is very important. A single board approach of the CCDU make the CCDU more reliable and less costly.
Claims12
A network enabled controller system for a combined centralized and distributed unit (CCDU) system, said system comprising:
- a housing for a controller, said controller operatively coupled to a processing unit of the CCDU, wherein the controller further comprises:
- an accelerator unit, said accelerator unit accelerates a set of functionalities of the CCDU;
- a fronthaul Network interface controller (NIC) (120), said fronthaul NIC is communicatively coupled with a radio unit (RU) (108);
- and
- a backhaul NIC communicatively coupled to a backhaul network (112);
- and
- and one or more network interfaces, wherein said controller including the accelerator unit, the fronthaul NIC, and the backhaul NIC is embedded in a single printed circuit board with the processing unit of the CCDU as a system on chip (SoC).
A method performed by a network enabled controller system for a combined centralized and distributed unit (CCDU) system, the method comprising:
- performing a combination of enhanced Common Public Radio Interface (eCPRI) and ORAN functionality;
- providing connectivity by a Backhaul NIC (114) with configured optical Ethernet;
- recovering, by a synchronization block equipped inside the Backhaul NIC (114), a Clock signal from the backhaul network (112);
- and
- supporting, by a Soft-Decision Forward Error Correction (SD-FEC) module (116), a Low Density Parity Check (LDPC) decoding and encoding and Turbo code decoding, wherein the SD-FEC module (116) is equipped inside an accelerator unit to give a confidence factor for deciding a signal between 1 and 0.
A non-transitory computer readable medium comprising processor executable instructions that cause a processor to:
- perform a combination of enhanced Common Public Radio Interface (eCPRI) and ORAN functionality;
- provide connectivity by a Backhaul NIC (114) with configured optical Ethernet;
- recover, by a synchronization block equipped inside the Backhaul NIC (114), a Clock signal from the backhaul network (112);
- and
- support, by a Soft-Decision Forward Error Correction (SD-FEC) module (116), a Low Density Parity Check (LDPC) decoding and encoding and Turbo code decoding, wherein the SD-FEC module (116) is equipped inside an accelerator unit to give a confidence factor for deciding a signal between 1 and 0.
Dependencies are inferred from the claim text.