Minimum euclidean distance finder and operating method thereof

A modem chip comprising:

• a common comparator configured to receive a first Euclidean distance (ED) set including an ED of each of n first symbol vector candidates from among a plurality of symbol vector candidates for a transmission symbol, wherein n is a natural number of 2 or greater, compare magnitudes of each potential combination of two EDs of the first ED set, and output first index information including results of comparing the magnitudes of the EDs of the first ED set;
• and
• an index-based ED finder configured to, for each bit in the transmission symbol:
• calculate each of a first minimum ED corresponding to a bit value of a corresponding bit being 1 and a second minimum ED of the bit value of the corresponding bit being 0, based on the first index information, and update the first minimum ED and the second minimum ED with a smallest first minimum ED and a smallest second minimum ED, respectively.

A minimum Euclidean distance (ED) finder comprising:

• a common comparator configured to receive a first ED set including an ED of each of four first symbol vector candidates from among a plurality of symbol vector candidates for a transmission symbol, compare magnitudes of the EDs of the first ED set, and output first index information and second index information, the first index information comprising a first magnitude comparison result of a first pair of EDs in the first ED set and a second magnitude comparison result of a second pair of EDs in the first ED set, and the second index information comprising magnitude comparison results of remaining pairs of EDs included in the first ED set;
• a first classifier configured to receive the first index information and bit values of the first pair of EDs for a first bit that is one of a plurality of bits of a plurality of layers of the transmission symbol, and output a first index related to the bit values of the first bit being 1 and a second index related to the bit values of the first bit being 0;
• a second classifier configured to receive the first index information and bit values of the second pair of EDs for the first bit, and output a third index related to the bit values of the second pair of EDs for the first bit being 1 and a fourth index related to the bit values of the second pair of EDs for the first bit being 0;
• a first index-based comparator configured to receive the second index information, the first index, and the third index, and output a fifth index indicating a first minimum ED corresponding to a bit value being 1 for the first bit;
• a second index-based comparator configured to receive the second index information, the second index, and the fourth index, and output a sixth index indicating a second minimum ED corresponding to the bit value being 0 for the first bit;
• a converter configured to convert the fifth index into the first minimum ED and the sixth index into the second minimum ED;
• and
• an iterative comparison circuit configured to update the first minimum ED and the second minimum ED.