Achieving high SSL/TLS throughput in embedded devices

An apparatus comprising:

• a hash message authentication code (HMAC) hardware, wherein the HMAC hardware is configured to:
• receive data in separate data transfers to perform a hash operation;
• receive data of unaligned lengths in the data the HMAC hardware receives, the data of unaligned lengths being smaller than a length of a transfer to the HMAC hardware;
• receive a residue indication to indicate to the HMAC hardware a number of bytes in the data of unaligned lengths without data for use by the HMAC hardware, the number of bytes constituting a residue;
• and
• fill in the residue from a subsequent data transfer responsive to the residue indication.

A system comprising:

• a hash message authentication code (HMAC) hardware, wherein the HMAC hardware is configured to:
• receive data in separate data transfers to compute a hash for message authentication;
• receive data of unaligned lengths in at least one of the separate data transfers, the data of unaligned lengths including a first number of bytes of valid data in a transfer having a second number of bytes, the second number of bytes being greater than the first number of bytes;
• receive an indication of a residue indicating a number of bytes without data in the data of unaligned lengths and fill in the residue from a subsequent data transfer responsive to the indication of the residue associated with the data of unaligned lengths;
• and
• receive, for each of the separate data transfers, an indication of whether the data is a final data transfer for computation of the hash or if more data is to be transferred after current data for computation of the hash and compute the hash responsive to the data being the final data transfer.