Back to results
US 12,627,317 B2Granted
Data encoding, data decoding, a semiconductor apparatus and a semiconductor system using the same
AssigneeSK hynix Inc.
InventorHyun Su Park
Life of this patent
Estimating the term…
Abstract
A data encoding method encodes eleven binary bits as seven symbols. The data encoding method generates a check signal based on first to fourth bits. The data encoding method includes encoding first to fifth bits to generate first to third symbols. The method includes encoding sixth to eighth bits to generate fourth and fifth symbols. The method also includes encoding ninth to eleventh bits to generate sixth and seventh symbols, when the check signal has a first logic level.
Claims33
A data encoding method, the method comprising:
- setting first to fifth bits as a first bit group, sixth to eighth bits as a second bit group, and ninth to eleventh bits as a third bit group;
- generating a check signal based on the first to fourth bits;
- and
- encoding the first to third bit groups based on the check signal and the fifth bit to generate first to seventh symbols,
- wherein when the check signal is at a first logic level, the first to third symbols are generated by encoding the first bit group, the fourth and fifth symbols are generated by encoding the second bit group, and the sixth and seventh symbols are generated by encoding the third bit group.
2 more elements
A data decoding method, the method comprising:
- setting first to third symbols as a first symbol group, fourth and fifth symbols as a second symbol group, and sixth and seventh symbols as a third symbol group;
- generating a check signal based on least significant bits of the fourth to seventh symbols;
- and
- decoding the first to third symbol groups based on the check signal and the least significant bits of the sixth and seventh symbols to generate first to eleventh bits,
- wherein when the check signal is at a first logic level, the first symbol group is decoded as the first to fifth bits, the second symbol group is decoded as the sixth to eighth bits, and the third symbol group is decoded as the ninth to eleventh bits.
2 more elements
A data encoding circuit comprising:
- a first encoding circuit configured to encode first to fifth bits to generate first to sixth encoding bits, configured to output one of the first and second encoding bits and the third and fourth encoding bits as a first symbol based on a check signal, and configured to output the third to sixth encoding bits and seventh to tenth encoding bits as a second symbol and a third symbol based on the check signal;
- a second encoding circuit configured to encode sixth to eighth bits to generate the seventh to tenth encoding bits, and configured to output one of the seventh to tenth encoding bits, eleventh to fourteenth encoding bits, and a fixed value as a fourth symbol and a fifth symbol based on the check signal and the fifth bit;
- a third encoding circuit configured to encode ninth to eleventh bits to generate the eleventh to fourteenth encoding bits, and configured to output one of the eleventh to fourteenth encoding bits and the fixed value as a sixth symbol and a seventh symbol based on a selection signal;
- a check logic circuit configured to generate the check signal based on the first to fourth bits;
- and
- a selection logic circuit configured to generate the selection signal based on the check signal and the fifth bit.
3 more elements
A data decoding circuit comprising:
- a first decoding circuit configured to decode first to third symbols to generate first to fifth decoding bits, configured to decode the first symbol to generate twelfth and thirteenth decoding bits, configured to output one of the first and second decoding bits and a fixed value as first and second bits based on a check signal, configured to output one of the third and fourth decoding bits and the twelfth and thirteenth decoding bits as third and fourth bits based on the check signal, and configured to output one of the fifth decoding bit and a logic bit as a fifth bit based on the check signal;
- a second decoding circuit configured to decode fourth and fifth symbols to generate sixth to eighth decoding bits, and configured to output one of the sixth to eighth decoding bits and the third to fifth decoding bits as sixth to eighth bits based on the check signal;
- a third decoding circuit configured to decode sixth and seventh symbols to generate ninth to eleventh decoding bits, and configured to output one of the ninth to eleventh decoding bits and the sixth to eighth decoding bits as ninth to eleventh bits based on a selection signal;
- and
- a control logic circuit configured to generate the check signal, the logic bit, and the selection signal based on least significant bits of the fourth to seventh symbols.
2 more elements
Dependencies are inferred from the claim text.