Analog-to-digital conversion circuit, receiver including the same, and timing calibration circuit
AssigneeSamsung Electronics Co., Ltd.
InventorsHyochul Shin, Sungno Lee, Junsang Park, Kyunghoon Lee
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Abstract
A analog-to-digital conversion circuit includes a plurality of time interleaved analog-digital converters (TI-ADCs), a timing calibrator configured to calculate calibration values of the plurality of TI-ADCs based on correlation values between target samples output from target TI-ADCs and adjacent samples of adjacent TI-ADCs in two respective cycles and output codes for calibrating time skews of the plurality of TI-ADCs based on the calibration values and a plurality of calibration parameters, and a clock phase adjuster configured to adjust phases of a plurality of clock signals based on the codes.
Claims20
An analog-to-digital conversion circuit comprising:
- a plurality of analog-digital converters (ADCs), each configured to sample an analog signal based on a clock signal in a time-interleaving manner;
- a timing calibrator circuit configured to
- calculate calibration values of the plurality of ADCs based on correlation values between target samples output from target ADCs from among the plurality of ADCs and adjacent samples output from adjacent ADCs adjacent to the target ADCs in two respective cycles,
- calculate a plurality of time skews regarding sampling timings of the plurality of ADCs based on the calibration values and a plurality of calibration parameters, and
- output codes for calibrating the plurality of time skews;
- and
- a clock phase adjuster circuit configured to adjust phases of a plurality of clock signals based on the codes, and provide adjusted phases of the plurality of clock signals to the plurality of ADCs.
A receiver comprising:
- an analog-to-digital conversion circuit configured to convert an analog signal to a digital signal;
- and
- an output circuit configured to improve quality of the digital signal,
- wherein the analog-to-digital conversion circuit comprises:
- a plurality of analog-digital converters (ADCs) each configured to sample an analog signal based on a clock signal in a time-interleaving manner;
- a timing calibrator circuit configured to calculate calibration values of the plurality of ADCs based on correlation values between target samples output from target ADCs from among the plurality of ADCs and adjacent samples of adjacent ADCs adjacent to the target ADCs in two respective cycles, calculate time skews regarding sampling timings of the plurality of ADCs based on the calibration values and a plurality of calibration parameters, and output codes for calibrating the time skews;
- and
- a clock phase adjuster configured to adjust phases of a plurality of clock signals to be provided to the plurality of ADCs based on the codes.
A timing calibration circuit comprising:
- auto-correlation calculators, each configured to calculate, based on a correlation value between target samples output from target time interleaved analog-to-digital converters (TI-ADCs) from among a plurality of TI-ADCs in two respective cycles and adjacent samples output from adjacent TI-ADCs mutually adjacent to the target TI-ADCs, calibration values of the target TI-ADCs selected in the two respective cycles;
- and
- a post-processor configured to calculate, based on the calibration values of the target TI-ADCs and a plurality of calibration parameters determined in advance, time skews regarding sampling timings of the target TI-ADCs.
Dependencies are inferred from the claim text.