Controlling and powering multiple chips
AssigneeAuradine, Inc.
InventorsShahriar Ilislamoo, David Carlson, Barun Kar, Darshan Shah
Life of this patent
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Abstract
An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.
Claims20
An electronic circuit, comprising:
- an event detector circuit;
- and
- a plurality of integrated circuit (IC) chips that are configured to respectively provide a plurality of output signals to the event detector circuit in parallel with one another,
- wherein the event detector circuit is configured to:
- receive the plurality of output signals from the plurality of IC chips,
- generate a data output signal that indicates toggling of a first output signal of the plurality of output signals, and
- transmit the data output signal to a computing device.
An electronic circuit, comprising:
- a plurality of integrated circuit (IC) chips that are configured to perform computations in parallel;
- and
- an event detector logic circuit that is electrically coupled to the plurality of IC chips and configured to:
- receive, from the plurality of IC chips, a plurality of output signals that are based on respective computations by the plurality of IC chips;
- generate a data output signal that includes data obtained from a first output signal of the plurality of output signals;
- and
- transmit the data output signal to a computing device.
An electronic circuit, comprising:
- a plurality of integrated circuit (IC) chips on a common circuit board, wherein the plurality of IC chips are electrically connected in parallel to at least one control bus configured to provide input signals, and
- wherein the plurality of IC chips comprise respective power inputs configured to receive a supply voltage from a power supply;
- and
- a plurality of isolation resistors electrically connected between at least one of:
- (i) a signal input of each of the plurality of IC chips and the at least one control bus, or
- (ii) the power input of each of the plurality of IC chips and the power supply.
Dependencies are inferred from the claim text.