Enhanced gain of operational amplifiers through low-frequency zero positioning
AssigneeThe Royal Institution for the Advancement of Learning/Mcgill University
InventorsMahmood A. Mohammed, Gordon Roberts
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Abstract
An amplifier circuit comprises a multi-stage amplifier having a plurality of amplifiers cascaded between an input port Vin and an output port Vout to form a differential input stage and N subsequent gain stages, a capacitive load CL coupled to the output port Vout, and a compensation network coupled to the multi-stage amplifier and configured for positioning Pole-Zero pairs of each stage of the multi-stage amplifier below a unity gain frequency ωt of the multi-stage amplifier when compensated, with Zeros positioned lower than Poles so as to increase the unity gain frequency ωt.
Claims18
An amplifier circuit comprising:
- a multi-stage amplifier having a plurality of amplifiers cascaded between an input port Vin and an output port Vout to form a differential input stage and N subsequent gain stages, with multiple Pole-Zero pairs arising from the N gain stages;
- a capacitive load CL coupled to the output port Vout;
- and
- a compensation network coupled to the multi-stage amplifier and configured for positioning, using at least one compensation resistor in a kΩ range, the Pole-Zero pairs of each stage of the multi-stage amplifier at a frequency below a unity gain frequency ωt of the multi-stage amplifier when compensated, with each Zero being positioned at a lower frequency than a corresponding Pole to increase the unity gain frequency ωt and increase a phase margin of the multi-stage amplifier.
Dependencies are inferred from the claim text.