Amplifier circuit having reset mechanism

An amplifier circuit having reset mechanism, comprising:

• a pair of upper-half branches electrically coupled between a first supply voltage and a pair of differential output terminals, wherein the pair of upper-half branches are symmetrical and each includes at least one P-type transistor, wherein the pair of upper-half branches are symmetrical and each comprises at least one P-type transistor;
• and
• a pair of lower-half branches electrically coupled between the pair of differential output terminals and a second supply voltage, wherein the lower-half branches are symmetrical and each comprises at least one N-type transistor;
• wherein the P-type transistors comprised by the upper-half branches and the N-type transistors comprised by the lower-half branches are categorized into a plurality of transistor groups such that the transistor groups in turn perform a differential signal receiving process in an interlaced manner under an interlaced input mode, and the transistor groups perform a reset signal receiving process when the differential signal receiving process is not performed to be turned on and be AC grounded such that the differential output terminals generate differential outputs;
• wherein each of the transistor groups includes M pairs of transistors each having a symmetrical input/output characteristic relative to the differential output terminals, M being a positive integer larger than or equal to 1.