An isolated power supply chip based on a symmetrical Class-D oscillator with dead zone control, with electromagnetic interference radiation caused by common-mode current suppressed, the isolated power supply chip comprising:
- a transmitting stage oscillator circuit connected to a power supply and a ground, wherein the transmitting stage oscillator circuit is configured to invert an input DC voltage into differential high-frequency oscillation power signals and input the differential high-frequency oscillation power signals to a primary coil of a subsequent transformer;
- a rectifier circuit connected to a secondary coil of the transformer and configured to rectify the differential high-frequency oscillation power signals to output a DC voltage signal;
- and
- a feedback control circuit connected to the rectifier circuit and configured to feed back the DC voltage signal to the transmitting stage oscillator circuit, so as to modulate and stabilize the DC voltage signal;
- wherein the transmitting stage oscillator circuit comprises:
- a dead zone control module, and a NMOS transistor group and a PMOS transistor group connected to the dead zone control module that are symmetrically arranged, the dead zone control module is configured to control a turn-on and a turn-off of the NMOS transistor group and the PMOS transistor group to eliminate a short circuit current between the power supply and the ground,
- wherein the NMOS transistor group comprises a first NMOS transistor and a second NMOS transistor, the PMOS transistor group comprises a first PMOS transistor and a second PMOS transistor, the dead zone control module comprises a first bias voltage, a second bias voltage, a first bias resistor, a second bias resistor, a third bias resistor, a fourth bias resistor, the first bias voltage is connected to a gate electrode of the first NMOS transistor through the first bias resistor, and is connected to a gate electrode of the second NMOS transistor through the second bias resistor;
- the second bias voltage is connected to a gate electrode of the first PMOS transistor through the third bias resistor, and is connected to a gate electrode of the second PMOS transistor through the fourth bias resistor, the first bias voltage and the second bias voltage satisfy:
- VBP−VBN>VDD−|VTHP|−VTHN
- wherein VBN represents the first bias voltage, VBP represents the second bias voltage, VDD represents a voltage of the power supply, VTHN represents a threshold voltage of the NMOS transistor group, VTHP represents a threshold voltage of the PMOS transistor group,
- wherein the drain electrode of the first NMOS transistor and the drain electrode of the first PMOS transistor are connected to a first end of the primary coil, and the drain electrode of the second NMOS transistor and the drain electrode of the second PMOS transistor are connected to a second end of the primary coil, so as to input the differential high-frequency oscillation power signals to the first end and the second end of the primary coil respectively.