US 12,626,776 B2 · Semiconductor memory device

Abstract

A semiconductor memory device includes an error bit detection unit and a bit counting unit. The error bit detection unit detects whether each bit in read data and each bit in expected data of the semiconductor memory device are consistent, and outputs the error bit data indicating pass/error information. The pass/error information indicates whether each detected bit is consistent. The bit counting unit counts the number of error bits in the error bit data indicating an inconsistency between the read data and the expected data, or counts the number of pass bits in the error bit data indicating consistency between the read data and the expected data. Furthermore, the semiconductor memory device also includes an interface for a read operation to input external expected values and an interface for the read operation interfaces to output the number of error bits or pass bits instead of the read data.

Claims20

Dependent claims

A semiconductor memory device, comprising:

an error bit detection unit, configured to detect whether each bit in read data and each bit in expected data of the semiconductor memory device are consistent, and configured to output error bit data that provides pass/error information, wherein each bit of the pass/error information is generated by a respective bitwise comparison circuit that receives one bit of the expected data and a corresponding bit of the read data, thereby causing each bit position of the pass/error information to indicate, on a one-to-one basis, whether a corresponding detected bit of the read data is consistent with the expected data;
and
a bit counting unit, configured to count a number of error bits in the error bit data that indicates that the read data and the expected data are inconsistent, or a number of pass bits in the error bit data that indicates that the read data and the expected data are consistent.

A semiconductor memory device, comprising:

an error bit detection unit, configured to detect whether each bit in read data and each bit in expected data of the semiconductor memory device are consistent, and configured to output error bit data that provides pass/error information, wherein the pass/error information indicates whether each detected bit is consistent;
a bit counting unit, configured to count a number of error bits in the error bit data that indicates that the read data and the expected data are inconsistent, or a number of pass bits in the error bit data that indicates that the read data and the expected data are consistent;
and
a bit counting differential amplifier, configured to input each bit of measurement object data including a plurality of bits and each bit of reference data including a plurality of bits, and to output a determination result (magnitude data) indicating a magnitude relationship between a number of bits in the measurement object data with a first logic level and a number of bits in the reference data with the first logic level.

1 more element

Dependencies are inferred from the claim text.

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims20