Nonvolatile memory devices and methods of controlling wordline erase operations within sub-blocks of memory strings

A method of controlling an erase operation of a nonvolatile memory device, the method comprising:

• dividing at least one memory block including a plurality of cell strings into a plurality of sub-blocks arranged in a vertical direction, each of the plurality of cell strings including:
• a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and arranged in the vertical direction between a bit-line and a common source line, wherein each of the plurality of sub-blocks includes at least one boundary word-line that is adjacent to another sub-block of the plurality of sub-blocks, and wherein each of the plurality of sub-blocks includes internal word-lines different from the at least one boundary word-line;
• applying a pre-program voltage with a first individual bias condition sequentially to the internal word-lines and the at least one boundary word-line of at least one sub-block to be erased from among the plurality of sub-blocks during a pre-program period of an erase loop, wherein the internal word-lines and the at least one boundary word-line are coupled to multi-level memory cells of the plurality of memory cells, which are configured to store data;
• and
• applying an erase voltage to a channel of the at least one memory block during an erase execution period of the erase loop.

A nonvolatile memory device comprising:

• at least one memory block including a plurality of cell strings, each of the plurality of cell strings including:
• a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and arranged in a vertical direction between a source line and a bit-line, wherein the at least one memory block is divided into a plurality of sub-blocks arranged in the vertical direction, with each of the plurality of sub-blocks including at least one boundary word-line that is adjacent to another sub-block and each of the plurality of sub-blocks including internal word-lines different from the at least one boundary word-line;
• and
• a control circuit configured to control an erase operation by:
• applying a pre-program voltage to word-lines of at least one sub-block to be erased from among the plurality of sub-blocks during a pre-program period of an erase loop, wherein the word-lines of the at least one sub-block are coupled to multi-level memory cells of the plurality of memory cells, which are configured to store data;
• applying an erase voltage to a channel of the at least one memory block during an erase execution period of the erase loop;
• and
• applying an erase verification voltage to at least one boundary word-line of the at least one sub-block to be erased during an erase verification period of the erase loop.