Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein

A memory device, comprising:

• a plurality of memory cells, wherein each memory cell of the plurality of memory cells has a respective variable impedance that varies in accordance with a respective data value stored therein, and
• a read circuit configured to
• count a clock signal and generate a clock at one or more predetermined count values, and
• read, using the clock generated at the one or more predetermined count values, the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the respective variable impedance of the selected memory cell,
• wherein the read circuit comprises a plurality of registers configured to receive the clock generated at the one or more predetermined count values,
• wherein the plurality of registers comprise a first register and a second register that are connected serially, and wherein an output of the first register is configured to drive an input of the second register;
• and
• wherein the read circuit is configured to effect a change in voltage of the signal node at a variable rate corresponding to the variable impedance of the selected memory cell, and to read the data value stored within the selected memory cell based upon the variable time delay determination of the signal node voltage change.