Semiconductor device having pad electrode equipped with low pass filter circuit
AssigneeMicron Technology, Inc.
InventorsNobuki Takahashi, Kohei Nakamura
Life of this patent
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Abstract
An example apparatus includes a passgate circuit between first and second nodes, the passgate circuit having a plurality of transistors at least two of which are operatively connected in parallel in a first mode and operatively connected in series in a second mode. The plurality of transistors may include first and second transistors coupled in parallel between the first and second nodes and controlled in common by a first control signal activated in the first mode. The plurality of transistors may further include third and fourth transistors connected in series between the first and second nodes and controlled in common by a second control signal activated in the second mode.
Claims18
An apparatus comprising a passgate circuit between first and second nodes, the passgate circuit having a plurality of transistors at least two of which are operatively connected in parallel in a first mode and operatively connected in series in a second mode, wherein the first node is coupled to a pad electrode supplied with a signal from outside;
- and an ODT circuit coupled to the pad electrode and deactivated in the second mode.
An apparatus comprising:
- an internal pad electrode;
- an input buffer circuit;
- an ODT circuit coupled to the internal pad electrode;
- and
- a passgate circuit including first and second signal paths operatively connected between the internal pad electrode and the input buffer circuit in parallel,
- wherein the first and second signal paths are different in resistance value from each other,
- wherein the first signal path is electrically connected between the internal pad electrode and the input buffer when a first control signal is activated and is electrically disconnected between the internal pad electrode and the input buffer when the first control signal is deactivated, and
- wherein the ODT circuit is deactivated when the first control signal is deactivated.
An apparatus comprising:
- a pad electrode;
- an input buffer circuit;
- an ODT circuit coupled to the pad electrode;
- and
- a passgate circuit including a first plurality of transistors coupled in parallel between the pad electrode and the input buffer circuit and a second plurality of transistors coupled in series between the pad electrode and the input buffer circuit,
- wherein the first plurality of transistors are brought into an ON state in a first mode, and
- wherein the second plurality of transistors are brought into an ON state and the ODT circuit is deactivated in a second mode.
An apparatus comprising a passgate circuit between first and second nodes, the passgate circuit having a plurality of transistors at least two of which are operatively connected in parallel in a first mode and operatively connected in series in a second mode, wherein the plurality of transistors includes first and second transistors coupled in parallel between the first and second nodes and controlled in common by a first control signal activated in the first mode, wherein the plurality of transistors further includes third and fourth transistors coupled in series between the first and second nodes and controlled in common by a second control signal activated in the second mode, and wherein the second control signal is deactivated in the first mode.
Dependencies are inferred from the claim text.