US 12,626,746 B2 · Method for manufacturing SRAM memory circuit

Abstract

A method includes forming a first transistor, a second transistor, a third transistor, and a fourth transistor over a substrate, wherein at least the second and third transistors include ferroelectric materials; forming an interlayer dielectric (ILD) layer over the first to fourth transistors; forming a first metal line over the ILD layer to interconnect drains of the second and third transistors and a gate of the fourth transistor; forming a second metal line over the ILD layer to interconnect a drain of the first transistor and gates of the second and third transistors; forming a write word line over the ILD layer and electrically connected to a gate of the first transistor but electrically isolated from the fourth transistor; forming a word line over the ILD layer and electrically connected to a source of the first transistor; and forming a bit line electrically connected to the fourth transistor.

Claims20

Dependent claims

A method for manufacturing an SRAM memory circuit, comprising:

forming a first MOSFET, a first FeFET, a second FeFET, and a second MOSFET over a substrate, wherein forming the first FeFET comprises:
forming a semiconductor fin over the substrate;
and
forming a gate structure over the semiconductor fin, wherein the gate structure comprises:
a ferroelectric layer over the semiconductor fin;
and
a gate electrode over the ferroelectric layer;
and
forming a plurality of interconnect layers over the first MOSFET, the first FeFET, the second FeFET, and the second MOSFET, wherein forming the plurality of interconnect layers comprises:
forming a first metal line over the substrate to interconnect a drain of the first MOSFET, the gate structure of the first FeFET, and a gate structure of the second FeFET;
and
forming a second metal line over the substrate to interconnect drains of the first FeFET and the second FeFET and a gate structure of the second MOSFET, such that the first MOSFET, the first FeFET, the second FeFET, the second MOSFET, and the plurality of interconnect layers form the SRAM memory circuit.

9 more elements

Dependencies are inferred from the claim text.

Method for manufacturing SRAM memory circuit

Life of this patent

Method for manufacturing SRAM memory circuit

Life of this patent

Abstract

Claims20