Systems and methods for ensuring high read reliability in pre-programmed memory cells

A method, comprising:

• configuring a read-only memory array and a multiplexer in communication with a differential sensing amplifier, the read-only memory array including a first subset of memory cells including a first memory cell storing a first logic value and a second subset of memory cells including a second memory cell storing a second logic value, the first memory cell including a first magnetic tunnel junction device having a fixed layer, a free layer, and a barrier layer positioned between the fixed layer and the free layer, the free layer having an antiparallel magnetic dipole orientation relative to the fixed layer such that the first memory cell exhibits a first resistance value and stores the first logic value, the configuring further comprising:
• configuring the read-only memory array to include a first plurality of bit lines and a second plurality of bit lines, the first plurality of bit lines including a first bit line coupled to the first memory cell and the second plurality of bit lines including a second bit line coupled to the second memory cell, and
• configuring the multiplexer to:
• (i) selectively establish electrical communication between a selected one of the first plurality of bit lines and a first input node of the differential sensing amplifier, and between a selected one of the second plurality of bit lines and a second input node of the differential sensing amplifier and, (ii) during a read operation of a selected bit value of the read-only memory array, to selectively couple the first bit line from the first plurality of bit lines to the first input node and the second bit line from the second plurality of bit lines to the second input node such that the first memory cell and the second memory cell together form a complementary cell pair that stores a single bit value of the read-only memory array;
• and
• applying a shorting voltage or current to the second memory cell of the second subset of memory cells of the read-only memory array, the second memory cell including a second magnetic tunnel junction device having a fixed layer, a free layer, and a barrier layer positioned between the fixed layer and the free layer, wherein the barrier layer of the second magnetic tunnel junction device is shorted such that the second memory cell permanently exhibits a second resistance value and maintains the second logic value;
• wherein the barrier layer of the second magnetic tunnel junction device being shorted and the free layer of the first magnetic tunnel junction device having the antiparallel magnetic dipole orientation relative to the fixed layer such that the first resistance value is greater than the second resistance value results in maximization of a differential voltage value between the first memory cell and the second memory cell during the read operation.

A memory system comprising:

• a read-only memory array, including:
• a first group of memory cells, each comprising a magnetic tunnel junction (MTJ) having an antiparallel magnetic dipole orientation and exhibiting a first resistance value;
• a second group of memory cells, each comprising an MTJ having a shorted barrier layer and exhibiting a second resistance value that is less than the first resistance value;
• a first plurality of bit lines, the first plurality of bit lines including a first bit line coupled to a first memory cell of a complementary cell pair, the first memory cell being a member of the first group of memory cells;
• and
• a second plurality of bit lines, the second plurality of bit lines including a second bit line coupled to a second memory cell of the complementary cell pair, the second memory cell being a member of the second group of memory cells;
• a differential sensing circuit including a differential sensing amplifier having a first input node and a second input node;
• and
• a mapping circuit including a first multiplexer configured to selectively couple a bit line of the first plurality of bit lines with the first input node of the differential sensing circuit, and a second multiplexer configured to selectively couple a bit line of the second plurality of bit lines with the second input node of the differential sensing circuit, the mapping circuit being further configured to associate respective memory cells of the first group of memory cells with corresponding memory cells of the second group of memory cells as complementary cell pairs, each respective complementary cell pair collectively storing a single bit value of the read-only memory array;
• and
• the differential sensing circuit configured to, for each complementary cell pair, bias the complementary cell pair via the first multiplexer and the second multiplexer such that a first signal at the first input node depends on the first resistance value and a second signal at the second input node depends on the second resistance value and to generate the bit value based on a comparison of a differential signal between the first and second signals with a reference current, wherein the antiparallel magnetic dipole orientation of the first group of memory cells and the shorted barrier layer of the second group of memory cells maximizes a magnitude of the differential signal relative to the reference current.