Write driver with selective voltage swing for memory devices

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines;
• a plurality of bitline sense amplifiers connected to the memory cell array through the plurality of bitlines;
• and
• a plurality of write drivers connected to the plurality of bitline sense amplifiers through a plurality of global input/output (I/O) lines, the plurality of write drivers configured to perform a write operation on the memory cell array,
• wherein each of the plurality of write drivers includes:
• a first pull-up circuit connected to an output terminal, the first pull-up circuit configured to pull up a voltage level of the output terminal based on a power supply voltage and a first pull-up control signal;
• a second pull-up circuit connected to the output terminal, the second pull-up circuit configured to pull up the voltage level of the output terminal based on the power supply voltage and a second pull-up control signal;
• and
• a pull-down circuit connected to the output terminal, the pull-down circuit configured to pull down the voltage level of the output terminal based on a ground voltage and a pull-down control signal, and
• wherein a first pull-up operation for pulling up the voltage level of the output terminal using the first pull-up circuit, and a second pull-up operation for pulling up the voltage level of the output terminal using the second pull-up circuit are selectively performed,
• wherein the plurality of memory cells include a first memory cell and a second memory cell,
• wherein the plurality of write drivers include a first write driver connected to the first memory cell, and a second write driver connected to the second memory cell, and
• wherein a length of a first time interval during which the first write driver performs the second pull-up operation and a length of a second time interval during which the second write driver performs the second pull-up operation are different from each other, depending on a first distance between the first memory cell and the first write driver and a second distance between the second memory cell and the second write driver.

A write driver configured to perform a write operation on a semiconductor memory device, the write driver comprising:

• a first n-type metal oxide semiconductor (NMOS) transistor connected between a power supply terminal receiving a power supply voltage and an output terminal connected to a global input/output (I/O) line, the first NMOS transistor including a gate electrode to which a first pull-up control signal is applied;
• a p-type metal oxide semiconductor (PMOS) transistor connected between the power supply terminal and the output terminal, the PMOS transistor including a gate electrode to which a second pull-up control signal is applied;
• a second NMOS transistor connected between the output terminal and a ground terminal receiving a ground voltage, the second NMOS transistor including a gate electrode to which a pull-down control signal is applied,
• wherein the write operation is an operation in which a plurality of data that are consecutive data are stored in the semiconductor memory device at once,
• wherein, in a time interval during which the plurality of data are provided, a first pull-up operation for pulling up a voltage level of the output terminal based on the power supply voltage and the first pull-up control signal is performed during a first portion of the time interval, a second pull-up operation for pulling up the voltage level of the output terminal based on the power supply voltage and the second pull-up control signal is performed during a second portion of the time interval subsequent to the first portion of the time interval, and a pull-down operation for pulling down the voltage level of the output terminal based on the ground voltage and the pull-down control signal is performed during the first portion of the time interval and the second portion of the time interval,
• wherein, in the first portion of the time interval, the PMOS transistor is disabled, and a voltage at the output terminal has a first swing width based on the first pull-up operation and the pull-down operation, and
• wherein, in the second portion of the time interval, the first NMOS transistor is disabled, and the voltage at the output terminal has a second swing width greater than the first swing width based on the second pull-up operation and the pull-down operation.