Memory, storage systems, and operation methods of memory
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsZhuangzhuang Wu, Ruxin Wei
Life of this patent
Estimating the term…
Abstract
Examples of the present disclosure provide a memory, a storage system, and an operation method of a memory. The memory includes: a plurality of memory planes and a peripheral circuit coupled to the memory planes. The peripheral circuit includes: a plurality of charge pumps, a charge pump having a clock signal end, an input end, and an output end, wherein the output end of each of the charge pumps is coupled to one of the plurality of memory planes; the charge pump is configured to boost an input voltage of the input end according to a clock signal received by the clock signal end and then output the same to the output end; wherein clock signals received by clock signal ends of the plurality of charge pumps are different.
Claims20
A memory, comprising:
- a plurality of memory planes;
- and
- a peripheral circuit coupled to the plurality of memory planes, comprising:
- a plurality of charge pumps, wherein each of the plurality of charge pumps has a clock signal end, an input end, and an output end, the output end of each of the plurality of charge pumps coupled to a memory plane of the plurality of memory planes, and each of the plurality of charge pumps is configured to boost an input voltage of the input end according to a first clock signal and a second clock signal received by the clock signal end and output the same to the output end, and wherein the first and second clock signals received by the clock signal ends of the plurality of charge pumps are different and there is a preset delay time between the first and second clock signals received by the clock signal ends;
- a clock generator configured to generate the first clock signal;
- and
- a clock processing circuit configured to delay the first clock signal with the preset delay time to generate the second clock signal different from the first clock signal based on the first clock signal.
A memory system, comprising:
- a memory, comprising:
- a plurality of memory planes;
- and
- a peripheral circuit coupled to the plurality of memory planes and comprising:
- a plurality of charge pumps, wherein each of the plurality of charge pumps has a clock signal end, an input end, and an output end, the output end of each of the plurality of charge pumps is coupled to a memory plane of the plurality of memory planes, and each of the plurality of charge pumps is configured to boost an input voltage of the input end according to a clock signal received by the clock signal end and output the same to the output end, and wherein the clock signals received by clock signal ends of the plurality of charge pumps are different;
- and
- a multiplexer coupled between the plurality of charge pumps and the plurality of memory planes, wherein, in an async multi-plane independent read operation, each of the plurality of charge pumps is coupled to the memory plane through the multiplexer, and, in a normal read operation, the plurality of charge pumps are connected in parallel through the multiplexer, and output ends of the plurality of charge pumps are coupled to an output node jointly;
- and
- a controller coupled to the memory and configured to control the memory.
An operation method of a memory, wherein the memory comprises a plurality of memory planes and a peripheral circuit coupled to the memory planes;
- the peripheral circuit comprises a plurality of charge pumps, a clock generator configured to generate a first clock signal, and a clock processing circuit configured to generate a second clock signal different from the first clock signal based on the first clock signal;
- a charge pump has a clock signal end, an input end, and an output end;
- and the output end of each of the charge pumps is coupled to one of the plurality of memory planes, and
- the operation method comprises:
- receiving, by clock signal ends of the plurality of charge pumps, the first and second clock signals;
- boosting input voltages of the input ends and then outputting the same to the output ends, in response to the first and second clock signals received by the clock signal ends;
- and
- delaying, by the clock processing circuit, the first clock signal with a preset delay time to generate the second clock signal, the preset delay time being a time between the first and second clock signals received by the clock signal ends.
Dependencies are inferred from the claim text.