Power management integrated circuit and memory module including the same

A power management integrated circuit (PMIC) comprising:

• an internal output transistor including a source terminal connected to an external voltage input line, to which an external voltage is supplied, and configured to output an internal output voltage to a voltage supply terminal of an external device in a normal mode and an overvoltage sensing mode;
• a self-overvoltage protection circuit configured to:
• turn on the internal output transistor in the overvoltage sensing mode, and
• turn off the internal output transistor in a clamp mode;
• and
• a clamp circuit including first and second high-voltage clamp transistors, which are connected to each other via a current mirror, and configured to output a clamp voltage as the internal output voltage, which is generated from the second high-voltage clamp transistor to the external device, in the clamp mode,
• wherein when the external voltage becomes higher than a first voltage, the PMIC is configured such that the self-overvoltage protection circuit turns on the internal output transistor, and
• wherein when the external voltage becomes higher than a second voltage greater than the first voltage, the PMIC is configured such that the self-overvoltage protection circuit turns off the internal output transistor.

A memory module comprising:

• memory input/output pins;
• a plurality of memory devices;
• and
• a power management integrated circuit (PMIC) configured to:
• receive an external voltage at an external voltage input line through at least one of the memory input/output pins, and
• output an internal output voltage to the plurality of memory devices,
• wherein the PMIC includes:
• an internal output transistor configured to turn on in a normal mode and an overvoltage sensing mode and provide the internal output voltage, and
• a clamp circuit including first and second high-voltage clamp transistors connected to each other via a current mirror, and configured to output a clamp voltage as the internal output voltage generated from the second high-voltage clamp transistor,
• wherein when the internal output transistor is turned off, the memory module is configured such that the clamp circuit outputs the clamp voltage from the second high-voltage clamp transistor.