Display driving device, processor, and electronic system

A display driving device comprising:

• a data receiving circuit configured to receive display data including image data and a synchronization signal from an external host;
• and
• an image scaling circuit configured to upscale resolution of the image data based on a plurality of horizontal synchronization signals included in the synchronization signal and transmitted at horizontal periods,
• the plurality of horizontal synchronization signals including a plurality of active synchronization signals transmitted in synchronization with a plurality of line image data corresponding to a plurality of horizontal lines included in the image data, and a plurality of blank synchronization signals unrelated to the plurality of line image data, wherein a number of the plurality of blank synchronization signals is equal to a number of horizontal lines of the upscaled resolution of the image data less a number of the plurality of horizontal lines included in the image data, and
• the image scaling circuit is configured to generate a plurality of additional line image data synchronized to the plurality of blank synchronization signals, based on at least one of the plurality of line image data transmitted in synchronization with at least one of the plurality of active synchronization signals.

A processor comprising:

• a storage configured to store scaling information received externally, wherein the scaling information includes a number of horizontal lines in a result image;
• a video timing circuit configured to generate a vertical synchronization signal and a horizontal synchronization signal based on the scaling information;
• a packet generating circuit configured to generate a plurality of data packets within one period of the vertical synchronization signal;
• and
• an image processing circuit configured to output an original image including a plurality of line image data arranged along a plurality of horizontal lines to the packet generating circuit
• wherein the packet generating circuit is configured to generate a portion of the plurality of data packets based on matching active synchronization signals included in the horizontal synchronization signal with the plurality of line image data, respectively, and generate a remainder of the plurality of data packets using blank synchronization signals included in the horizontal synchronization signal, wherein a number of the blank synchronization signals is equal to the number of the horizontal lines in the result image less a number of the plurality of horizontal lines in the original image.