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US 12,626,114 B2Granted
Discrete three-dimensional processor
AssigneeHong Kong HaiCun Technology Co., Limited
InventorGuobiao Zhang
Life of this patent
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Abstract
A discrete three-dimensional (3-D) processor comprises a plurality of storage-processing units (SPU's), each of the SPU's comprising a non-memory circuit, at least a memory array and at least an off-die peripheral-circuit component thereof. The 3-D processor further comprises first and second dice. The first die comprises the memory arrays, whereas the second die comprises the non-memory circuit and the off-die peripheral-circuit component.
Claims32
A discrete three-dimensional (3-D) processor, comprising:
- a plurality of storage-processing units (SPU's), wherein each of said plurality of SPU's comprises a non-memory circuit, at least a memory array and an off-die peripheral-circuit component thereof;
- a first die including 3-D structures, further comprising the memory arrays of said plurality of SPU's;
- a second die including only 2-D circuits, further comprising the nonmemory circuits and the off-die peripheral-circuit components of said plurality of SPU's;
- a plurality of inter-die connections between said first and second dice communicatively coupling the memory arrays with the off-die peripheral-circuit components and the non-memory circuits of said plurality of SPU's;
- wherein said non-memory circuit is not a part of any memory;
- and, said an off-die peripheral-circuit component is not an input/output (I/O) circuit.
3 more elements
Dependencies are inferred from the claim text.