High-speed pulse-width modulator

A device comprising:

• a processor configured to split input digital bits into a first part and a second part;
• a digital-to-analog converter (DAC) coupled with the processor, and configured to encode the first part and the second part into analog form as an activation pulse having width equivalent to magnitude of the first part in time units and a delay of a duration that is a fraction of one time unit of the time units, the fraction being equivalent to magnitude of the second part divided by two raised to power of number of bits in the second part;
• a crossbar array coupled with the DAC, and structured with resistive memory devices, the crossbar array configured to store weights, wherein each of the weights is encoded as analog conductance using at least one of the resistive memory devices, the crossbar array configured to generate analog computation output responsive to the analog form of the input digital bits applied to the crossbar array;
• and
• an analog-to-digital converter (ADC) coupled with the crossbar array, and configured to digitize the analog computation output from the crossbar array.