Cache control to preserve register data

A method, comprising:

• storing, by a computing system in an operand cache, register operand data for operations performed by a processor pipeline of the computing system;
• controlling, by the computing system, a first set of lock indicators for a set of registers for a first thread, including to assert one or more lock indicators for registers that are indicated as being utilized by instructions of the first thread;
• preserving, by the computing system, register operand data in a data cache, including to prevent eviction of a given cache line from the data cache based on an asserted lock indicator for register data stored in the given cache line;
• and
• in response to a reset event, the computing system:
• flushing operand data to the data cache from one or more entries of the operand cache indicated as being last-use;
• and
• clearing the first set of lock indicators.

An apparatus, comprising:

• processor pipeline circuitry configured to perform operations on register operand data;
• control circuitry configured to provide memory backing for register operand data in a memory hierarchy, wherein the memory hierarchy includes a data cache at a first cache level;
• scoreboard circuitry configured to track which architectural registers are stored at the first cache level;
• and
• lock circuitry configured to:
• initiate a map request to confirm whether operand data for registers that are indicated as being utilized by instructions of a first thread are stored at the first cache level;
• in response to the scoreboard circuitry confirming that one or more registers utilized by instructions of the first thread are stored at the first cache level, control a first set of lock indicators for a set of registers for the first thread, including to assert one or more lock indicators corresponding to the confirmed one or more registers;
• and
• preserve register operand data in the data cache, including to prevent eviction of a given cache line from the data cache based on an asserted lock indicator for a register stored in the given cache line.