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US 12,625,809 B2Granted
Cache coherence shared state suppression
AssigneeTexas Instruments Incorporated
InventorsAbhijeet Ashok Chachad, David Matthew Thompson, Timothy David Anderson, Kai Chirca
Life of this patent
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Abstract
A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.
Claims20
A device, comprising:
- a cache memory;
- and
- a cache controller associated with the cache memory and configured to:
- store a value that specifies whether the cache controller is configured to operate in a first mode or a second mode, wherein a first coherence state is supported in the first mode and not supported in the second mode;
- receive a first cache request associated with the first coherence state;
- and
- determine whether to generate, in response to the first cache request, a second cache request associated with the first coherence state or associated with a second coherence state based on the value.
4 more elements
A method, comprising:
- storing, by a cache controller, a value that specifies whether the cache controller is configured to operate in a first mode or a second mode, wherein a first coherence state is supported in the first mode and not supported in the second mode;
- receiving, by the cache controller, a first cache request associated with the first coherence state;
- and
- determining, by the cache controller, whether to generate, in response to the first cache request, a second cache request associated with the first coherence state or associated with a second coherence state based on the value.
1 more element
Dependencies are inferred from the claim text.