Memory systems, operation methods thereof, and computer-readable storage mediums to detect an abnormality in firmware
AssigneeYangtze Memory Technologies Co., Ltd.
InventorZhebo Wu
Life of this patent
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Abstract
The present disclosure provides a memory system, an operation method thereof, and a computer-readable storage medium. The memory system includes: a memory device and a memory controller coupled with the memory device. The memory system includes a general-purpose input/output interface including a first pin that is configurable to receive data transmitted by serial communication. The memory controller is configured to: trigger an interruption by the first pin in response to abnormality of a firmware of the memory system during operation; and trigger an assert dump mode in response to the interruption triggered by the first pin.
Claims20
A memory system, comprising a memory device and a memory controller coupled with the memory device, and the memory system further including a general-purpose input/output interface, wherein the general-purpose input/output interface includes a first pin that is configurable to receive data transmitted by serial communication, and the memory controller is configured to:
- detect a change in a signal level of the first pin, wherein to detect the change in the signal level the first pin is configured to a first mode:
- trigger an interruption by the first pin in response to an abnormality of a firmware of the memory system during operation, wherein the interruption is triggered in response to the signal level of the first pin satisfying a threshold and causing the first pin to switch from the first mode to trigger the interruption;
- and
- trigger an assert dump mode in response to the interruption triggered by the first pin, wherein, after triggering the assert dump mode, the first pin is configured to a second mode to receive the data transmitted by serial communication.
An operation method of a memory system, comprising:
- detecting a change in a signal level of a first pin of a general-purpose input/output interface of the memory system that is configurable to receive data transmitted by serial communication, wherein to detect the change in the signal level the first pin is configured to a first mode;
- triggering an interruption by the first pin in response to an abnormality of a firmware of the memory system during operation, wherein the interruption is triggered in response to the signal level of the first pin satisfying a threshold and causing the first pin to switch from the first mode to trigger the interruption;
- and
- triggering an assert dump mode in response to the interruption triggered by the first pin, wherein, after triggering the assert dump mode, the first pin is configured to a second mode to receive the data transmitted by serial communication.
Dependencies are inferred from the claim text.