Quadrature error correction circuit and memory device having the same

A memory device comprising:

• a clock receiver configured to receive an external clock signal;
• a transmitter configured to receive a plurality of data in parallel and sequentially output the plurality of data based on a plurality of clock signals having a same frequency as the external clock signal, each one of the plurality of clock signals having a phase different from another one of the plurality of clock signals;
• and
• a quadrature error correction (QEC) circuit configured to:
• selectively receive a first clock signal among the plurality of clock signals, the first clock signal having a first phase,
• generate a second clock signal based on a delay operation with respect to the first clock signal, the second clock signal having a second phase different from the first phase of the first clock signal, and
• correct a skew between the plurality of clock signals by performing a phase comparison between the plurality of clock signals generated based on the first clock signal and second clock signal,
• wherein the plurality clock signals comprise a first clock signal, a second clock signal, a third clock signal and a fourth clock signal which have a sequential phase difference of 90 degrees in this order, and
• wherein the QEC circuit comprises:
• a first delayer configured to output the second clock signal by performing a first quad delay operation on the first clock signal;
• a control code storage configured to store a first control code generated based on the phase comparison between the plurality of clock signals;
• and
• an edge controller configured to receive the first clock signal and the second clock signal, and control at least one of a first rising edge and a first falling edge of the first clock signal and at least one of a second rising edge and a second falling edge of the second clock signal based on the first control code.

A memory device comprising:

• a clock receiver configured to receive an external clock signal;
• a transmitter configured to receive a plurality of data in parallel and sequentially output the plurality of data based on a plurality of clock signals having a same frequency as the external clock signal, each one of the plurality of clock signals having a phase different from another one of the plurality of clock signals;
• and
• a quadrature error correction (QEC) circuit configured to:
• selectively receive a first clock signal among the plurality of clock signals, the first clock signal having a first phase,
• generate a second clock signal based on a delay operation with respect to the first clock signal, the second clock signal having a second phase different from the first phase of the first clock signal, and
• correct a skew between the plurality of clock signals by performing a phase comparison between the plurality of clock signals generated based on the first clock signal and second clock signal,
• wherein the clock receiver is configured to receive a differential clock signal comprising the external clock signal and an inversion signal of the external clock signal,
• wherein the plurality of clock signals comprise the first clock signal, the second clock signal, a third clock signal and a fourth clock signal which have a sequential phase difference of 90 degrees in this order, and
• wherein the memory device further comprises:
• a buffer configured to output the first clock signal and an inversion signal of the first clock signal based on a buffer operation on the differential clock signal;
• a multiplexer configured to selectively output the first clock signal among the first clock signal and the inversion signal of the first clock signal;
• and
• a phase locked loop configured to perform a phase locked loop operation on the first clock signal and provide the first clock signal to the QEC circuit.