High-speed transmitter circuit system for attenuating inter-channel interference

An inter-channel interference attenuation circuit system comprising:

• a plurality of channels provided between a memory and a processor and configured to transmit data received from the memory to the processor;
• and
• an interference attenuation circuit module connected one by one to each of the channels, and
• wherein each of the channels is:
• a victim channel with respect to the connected interference attenuation circuit module;
• and
• an aggressive channel with respect to an adjacent interference attenuation circuit module, which is an interference attenuation circuit module connected to an adjacent channel which is interfered with by its own data transmission, and
• each of the interference attenuation circuit modules is configured to:
• adjust an output signal of the connected victim channel based on the interference attenuation circuit module and the number of adjacent channels which are aggressive channels with respect to the victim channel and whose transmitted data changes from ‘0’ to ‘1’;
• and
• adjust the output signal of the connected victim channel based on the interference attenuation circuit module and the number of adjacent channels which are aggressive channels with respect to the victim channel and whose transmitted data changes from ‘1’ to ‘0’, and
• wherein the each of the interference attenuation circuit modules is configured to:
• receive an encoder input signal generated by the data transmission of the each aggressive channel from the adjacent interference attenuation circuit module connected to at least one aggressive channel with respect to the connected victim channel;
• and
• adjust the output signal of the connected victim channel based on the at least one received encoder input signal.