Correctly rounded table-based computation of logarithmic function

A processing apparatus with increased efficiency in computation of correctly-rounded logarithm value in specialized hardware, comprising:

• an input interface configured to receive a number;
• at least one processor which comprises one or more interconnected computing grids, wherein each of the one or more interconnected computing grid comprises a plurality of reconfigurable logical elements connected to a plurality of memory units via an interconnected network comprising:
• a plurality of configurable data routing junctions, a plurality of ingress ports, and a plurality of egress ports;
• one or more unsigned integer arithmetic circuits of the at least one processor configured to:
• compute off-line or compute in advance to real-time computation of a logarithm value for the received number, a plurality of pre-computed logarithm values and corresponding inverse values of the pre-computed logarithm values, each for another one of a plurality of breakpoint values;
• store said plurality of pre-computed logarithm values and said corresponding inverse values in a memory device;
• in run-time:
• during each of a plurality of executed computation tasks, analyze each respective computation task to determine computational requirements and dynamically adjust a configuration of the one or more interconnected computing grids by:
• creating a directed acyclic compute graph having nodes corresponding to logarithmic operations and edges corresponding to data movement between operations, mapping said nodes to said reconfigurable logical elements, and configuring said configurable data routing junctions to connect said nodes according to said edges of said compute graph via said plurality of ingress ports and said plurality of egress ports for an optimized processing configuration, said plurality of executed computation tasks comprising:
• compute an exponent and significand of the received number;
• select a breakpoint value from the plurality of breakpoint values segmenting a range of the significand, the selected breakpoint value is one of:
• a greatest lower bound, and a lowest upper bound, of the significand;
• fetch from said memory device a respective logarithm value of the selected breakpoint value;
• compute a multiplication of the exponent and a logarithm value of two;
• compute a first intermediate value based on a least significant portion of the significand and an inverse value of the selected breakpoint value;
• compute an approximated logarithm value of a second intermediate value derived from the first intermediate value;
• compute a logarithm value of the significand by summing the approximated logarithm value and the fetched respective logarithm value of the selected breakpoint value;
• compute the logarithm value of the received number by summing the logarithm value of the significand and the multiplication of the exponent and the logarithm value of two;
• and
• an output interface configured to output the correctly-rounded logarithm value computed for the received number
• wherein storing said pre-computed logarithm values and inverse values in said memory device enables fetching of pre-computed values rather than computing inverse values and logarithm values during execution of the computation tasks, thereby reducing hardware resource utilization and power consumption.

A method for efficiently computing correctly-rounded logarithm value in specialized hardware, comprising:

• using one or more unsigned integer arithmetic circuits of at least one processor configured for:
• computing off-line or computing in advance to real-time computation of a logarithm value for a received number, a plurality of pre-computed binary logarithm values and corresponding inverse values of the pre-computed binary logarithm values, each for another one of a plurality of breakpoint values;
• storing said plurality of pre-computed binary logarithm values and said corresponding inverse values in a memory device;
• wherein said at least one processor comprises one or more interconnected computing grids, wherein each of the one or more interconnected computing grid comprises a plurality of reconfigurable logical elements connected to a plurality of memory units via an interconnected network comprising:
• a plurality of configurable data routing junctions, a plurality of ingress ports, and a plurality of egress ports;
• in run-time:
• during each of a plurality of executed computation tasks, analyzing each respective computation task to determine computational requirements and dynamically adjusting a configuration of the one or more interconnected computing grids by:
• creating a directed acyclic compute graph having nodes corresponding to logarithmic operations and edges corresponding to data movement between operations, mapping said nodes to said reconfigurable logical elements, and configuring said configurable data routing junctions to connect said nodes according to said edges of said compute graph via said plurality of ingress ports and said plurality of egress ports for an optimized processing configuration, said plurality of executed computation tasks comprising:
• receiving, through an I/O interface, a number and computing, by said logarithm calculator, an exponent and significand of the received number;
• selecting a breakpoint value from the plurality of breakpoint values segmenting a range of the significand, the selected breakpoint value is one of:
• a greatest lower bound, and a lowest upper bound, of the significand;
• fetching from said memory device a respective binary logarithm value of the selected breakpoint value;
• computing a first intermediate value based on a least significant portion of the significand and an inverse value of the selected breakpoint value;
• computing an approximated binary logarithm value of a second intermediate value derived from the first intermediate value;
• computing a binary logarithm value of the significand by summing the approximated binary logarithm value and the fetched respective binary logarithm value of the selected breakpoint value;
• computing a binary logarithm value of the received number by summing the binary logarithm value of the significand and the exponent;
• computing a base b logarithm value of the received number by dividing the binary logarithm value of the received number by a binary logarithm value of b;
• and
• outputting, through said I/O interface, the correctly-rounded logarithm value,
• wherein storing said pre-computed logarithm values and inverse values in said memory device enables fetching of pre-computed values rather than computing inverse values and logarithm values during execution of the computation tasks, thereby reducing hardware resource utilization and power consumption.