US 12,622,318 B2 · Wafer to wafer high density interconnects

Abstract

An integrated circuit package provides a high bandwidth interconnect between wafers using a very high density interconnect using a silicon bridge or a multi-layer flex between wafers. In some embodiments, more than one wafer may be mounted and connected with a rigid silicon bridge onto a common substrate. This common substrate can be matched, with respect to their coefficients of thermal expansion (CTE), to the silicon wafer. The CTE matched substrate can reduce the thermal mechanical stress on the wafers and the rigid silicon bridge interconnect. In some embodiments, a thinned silicon bridge is utilized to interconnect wafers which are mounted on separate glass substrates. The thinned bridge would allow for mechanical compliance between the wafers. In some embodiments, the wafers can be mounted onto separate glass substrates and attached with a fine pitch multi-layer flex structure which provides compliance between the wafers.

Claims20

Dependent claims

A wafer scale system, comprising:

a plurality of wafers mounted on a substrate, wherein
the plurality of wafers comprises a first wafer and a second wafer,
the first wafer is adjacent to the second wafer, and
each of the first wafer and the second wafer comprises a plurality of die sites;
and
a high density interconnect structure that comprises a plurality of signal wires, wherein each signal wire of the plurality of signal wires connects one or more die sites of the plurality of die sites of the first wafer to one or more die sites of the plurality of die sites of the second wafer.

3 more elements

Dependencies are inferred from the claim text.

Wafer to wafer high density interconnects

Life of this patent

Wafer to wafer high density interconnects

Life of this patent

Abstract

Claims20