Low-stress passivation layer

A method, comprising:

• providing a substrate including a redistribution layer disposed over a multi-layer interconnect (MLI) structure;
• depositing a nitride layer over the redistribution layer;
• and
• forming a recess extending through the nitride layer and the redistribution layer, wherein the recess separates a first portion of the redistribution layer from a second portion of the redistribution layer, and wherein the forming the recess includes an etching process that provides a rounding of a corner of at least one of the first portion of the redistribution layer and the second portion of the redistribution layer on either side of the recess;
• wherein after forming the recess, the nitride layer remains disposed over top surfaces of the first portion of the redistribution layer and the second portion of the redistribution layer, while sidewall surfaces of the first portion of the redistribution layer and the second portion of the redistribution layer are free of the nitride layer.

A semiconductor device, comprising:

• a redistribution layer including a first conductive feature and a second conductive feature separated by a recess, wherein corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess;
• a first passivation layer disposed over the redistribution layer and within the recess;
• and
• a contact feature extending through the first passivation layer and electrically coupled to the first conductive feature;
• wherein the first passivation layer includes a nitride layer having a discontinuity region that is substantially aligned with the corners of the first conductive feature and the second conductive feature, wherein the first passivation layer further includes a first dielectric layer interposing the redistribution layer and the nitride layer along upper sidewall portions of the recess and along top surfaces of the first and second conductive features, and wherein the first dielectric layer further interposes a second passivation layer underlying the redistribution layer and the nitride layer along lower sidewall portions of the recess and along a bottom surface of the recess;
• and
• wherein a top surface of the first conductive feature defines a first plane, wherein a sidewall of the first conductive feature adjacent to the recess defines a second plane that intersects the first plane, and wherein a rounding of the corner of the first conductive feature is defined at least partly by a distance between the intersection of the first and second planes and a surface of the corner of the first conductive feature.