Self-aligned staggered integrated circuit interconnect features

An integrated circuit (IC) structure, comprising:

• a device layer comprising a plurality of transistors or memory cells;
• and
• an interconnect structure electrically coupled the device layer, wherein the interconnect structure further comprises:
• a plurality of first interconnect lines with spaces therebetween;
• a dielectric material over the first interconnect lines and within the spaces, wherein topography in the dielectric material defines a plurality of trenches between the first interconnect lines;
• and
• a plurality of second interconnect lines interdigitated with the first interconnect lines, wherein the second interconnect lines occupy at least a portion of each of the trenches between individual ones of the first interconnect lines, comprise predominantly W, Ru, Mo, or Co, and wherein a top surface of a first length of the one of the second interconnect lines is below a top surface of a second length of the one of the second interconnect lines.

A method of fabricating an interconnect structure, the method comprising:

• forming first interconnect lines;
• forming trenches staggered from the first interconnect lines by super-conformally depositing a non-planar dielectric material layer over the first interconnect lines and within spaces therebetween;
• depositing metallization over a non-planar surface of the dielectric material layer;
• and
• forming parallel second interconnect lines by planarizing the metallization within the trenches with ridges of the non-planar dielectric material layer between the trenches, wherein bottoms of the second interconnect lines are vertically offset above bottoms of the first interconnect lines by a first thickness of the dielectric material that is greater than a second thickness of the dielectric material between nearest edges of adjacent ones of the first and second interconnect line.