Structure and method for test-point access in a semiconductor

Method of enabling a circuit editing (CE) tool to physically probe a semiconductor using a test-point access structure:

• wherein the test-point access structure comprises,
• a target test-point configured to be coupled to a circuit within the semiconductor;
• a first doped region within the semiconductor;
• a second doped region within the semiconductor;
• a target pad coupling the target test-point to the first doped region;
• and
• wherein the method comprises,
• distributing a set of instructions, stored on a non-transitory, tangible computer readable storage medium, for configuring the circuit editing (CE) tool;
• wherein the instructions include,
• transmitting an energy beam from the circuit editing (CE) tool;
• measuring a first signal from the first doped region generated in response to the energy beam;
• measuring a second signal from the second doped region generated in response to the energy beam;
• and
• removing material from the semiconductor in response to the first signal and the second signal;
• wherein when the first signal exceeds a threshold value, then the CE tool is configured to stop removing a first set of material having a first cross-sectional area from the semiconductor;
• and
• wherein when the second signal exceeds a threshold value the CE tool is configured to stop removing a second set of material having a second cross-sectional area from the semiconductor.

A test-point access structure within a semiconductor, the structure comprising:

• a target test-point configured to be coupled to a circuit within the semiconductor;
• a first doped region within the semiconductor configured to generate a first signal in response to an energy beam transmitted by a circuit editing (CE) tool;
• a second doped region within the semiconductor configured to generate a second signal in response to the energy beam transmitted by the CE tool;
• and
• a target pad coupling the target test-point to the first doped region;
• a void having an area defined by an amount of material removed by the CE tool in response to the first signal and the second signal;
• wherein the test-point access structure is placed in a spare tiling region of the semiconductor.