Method of making breakdown resistant semiconductor device

A method of manufacturing a semiconductor device, comprising:

• doping an entirety of a first channel region of a first transistor with a first dopant having a first conductivity type, wherein doping the first channel region comprises doping the first channel region of a nanowire field effect transistor (NWFET);
• doping an entirety of a second channel region of a second transistor with a second dopant having the first conductivity type;
• forming first source/drain regions of the first transistor to have the first conductivity type, and the channel region of the first transistor is an entire area between the first source/drain regions configured to permit current flow in response to a gate of the first transistor receiving a threshold voltage, wherein a depth of the first channel region is equal to or greater than a depth of the first source/drain regions;
• forming second source/drain regions of the second transistor to have a second conductivity type, wherein the second conductivity is different from the first conductivity type;
• forming a well having the second conductivity type, wherein the first channel region is between a bottommost surface of the first source/drain regions and the well;
• forming a first gate electrode over the first channel region, wherein the first gate electrode comprises a first material;
• and
• forming a second gate electrode over the second channel region, wherein the second gate electrode comprises the first material.

A method of manufacturing a semiconductor device, comprising:

• doping an entirety of a first channel region of a first transistor with a first dopant having a first conductivity type;
• doping an entirety of a second channel region of a second transistor with a second dopant having the first conductivity type;
• growing first source/drain regions of the first transistor, wherein the channel region of the first transistor is an entire area between the first source/drain regions configured to permit current flow in response to a gate of the first transistor receiving a threshold voltage, wherein a depth of the first channel region is equal to or greater than a depth of the first source/drain regions;
• doping first source/drain regions to have the first conductivity type;
• forming second source/drain regions of the second transistor to have a second conductivity type, wherein the second conductivity is different from the first conductivity type;
• forming a well having the second conductivity type, wherein the first channel region is between a bottommost surface of the first source/drain regions and the well;
• depositing a first work function layer over the first channel region;
• and
• depositing a second work function layer over the second channel region, wherein the first work function layer and the second work function layer comprise a same material.