MV device and method for manufacturing same

A method for manufacturing a medium voltage (MV) device, comprising:

• step 1, providing a semiconductor substrate, forming two lightly doped drain regions in selected regions of the semiconductor substrate;
• forming a channel region in a surface of the semiconductor substrate between the two lightly doped drain regions;
• step 2, forming a gate dielectric layer on the surface of the semiconductor substrate;
• step 3, growing a gate conductive material layer on a surface of the gate dielectric layer;
• performing a first patterning on the gate conductive material layer to form side faces on the gate conductive material layer and a segmentation trench on each side;
• and
• dividing the gate conductive material layer into a body gate conductive material layer and two edge gate conductive material layers along a channel length direction, wherein the body gate conductive material layer is located in a middle region, the two edge gate conductive material layers are located on two sides of the body gate conductive material layer, and wherein the two edge gate conductive material layers each is spaced apart from the body gate conductive material layer by the segmentation trench;
• wherein a first side face and a second side face of the gate conductive material layer are outer surfaces of the edge gate conductive material layers and located along the channel length direction;
• wherein the lightly doped drain regions extend under the first side face and the second side face of the gate conductive material layer, to reach under the body gate conductive material layer, such that the channel region becomes located under the body gate conductive material layer;
• and
• wherein the edge gate conductive material layers become located above the lightly doped drain regions;
• step 4, forming spacers on side faces of the gate conductive material layer;
• step 5, filling each segmentation trench with a dielectric segmentation structure, wherein forming the dielectric segmentation structure comprises forming a first dielectric layer of the spacers, wherein the first dielectric layer does not fully fill the segmentation trench and leaves a gap in the segmentation trench;
• and forming a second dielectric layer to fill the gap of the segmentation trench;
• wherein the first dielectric layer and the second dielectric layer are stacked in the segmentation trench;
• and
• step 6, forming source drain implantation regions in a self-aligned process on surfaces of the lightly doped drain regions outside the spacers away from the first side face and the second side face of the gate conductive material layer.