Silicon carbide transistor with channel counter-doping and pocket-doping

A silicon carbide transistor comprising:

• a source region;
• a drain region;
• a gate oxide;
• and
• a channel region between the source region and the drain region and beneath the gate oxide, wherein the channel region comprises:
• a p-doped silicon carbide region beneath the gate oxide;
• a counter-doped region comprising n-doped silicon carbide, wherein the counter-doped region is between the p-doped silicon carbide region and the gate oxide;
• a first p-doped pocket region between the source region and the counter-doped region;
• and
• a second p-doped pocket region between the drain region and the counter-doped region.

A method of forming a channel region for a silicon carbide transistor, the method comprising:

• providing a silicon carbide layer;
• implanting a p-dopant in the silicon carbide layer to form a p-doped region that is doped at a concentration greater than or about 1e18 cm3 between a source region and a drain region;
• implanting an n-dopant in the silicon carbide layer to form a counter-doped region comprising n-doped silicon carbide between the source region and the drain region, wherein the counter-doped region is on top of the p-doped region;
• and
• implanting a first p-doped pocket region between the source region and the counter-doped region.