Back to results
US 12,622,021 B2Granted
Semiconductor structure with conductive spacer in shallow trench isolation region
AssigneeInternational Business Machines Corporation
InventorsKoichi Motoyama, Ruilong Xie, Kisik Choi, Chih-Chao Yang
Life of this patent
Estimating the term…
Abstract
A semiconductor structure includes a shallow trench isolation region disposed within a semiconductor substrate, and a conductive spacer disposed within the shallow trench isolation region.
Claims20
A semiconductor structure, comprising:
- a shallow trench isolation region disposed within a semiconductor substrate;
- a conductive spacer disposed within the shallow trench isolation region;
- and
- a backside power rail disposed on a bottom surface of the conductive spacer;
- wherein a bottom surface of the conductive spacer is coplanar with a bottom surface of the shallow trench isolation region.
2 more elements
A semiconductor structure, comprising:
- a plurality of shallow trench isolation regions disposed within a semiconductor substrate;
- a conductive spacer disposed within one of the plurality of shallow trench isolation regions;
- and
- a via-to-backside power rail disposed on a top surface of the conductive spacer;
- wherein the top surface of the conductive spacer is coplanar with a top surface of the one of the plurality of shallow trench isolation regions;
- and
- wherein the conductive spacer has a first width and the via-to-backside power rail has a second width less than the first width.
4 more elements
A semiconductor structure, comprising:
- a plurality of shallow trench isolation regions disposed within a semiconductor substrate;
- a conductive spacer disposed within one of the plurality of shallow trench isolation regions;
- a plurality of stacked nanosheet channel layers located above the semiconductor substrate and between respective shallow trench isolation regions;
- and
- a via-to-backside power rail disposed on a top surface of the conductive spacer;
- wherein the top surface of the conductive spacer is coplanar with a top surface of the one of the plurality of shallow trench isolation regions;
- and
- wherein the conductive spacer has a first width and the via-to-backside power rail has a second width less than the first width.
5 more elements
Dependencies are inferred from the claim text.