DMOS device having junction field plate and manufacturing method therefor

A method of manufacturing a DMOS device with a junction field plate, the method comprising:

• providing a semiconductor substrate, in which a first trench is formed;
• forming a first doped polycrystalline silicon layer with a first conduction type on the semiconductor substrate, wherein the first doped polycrystalline silicon layer covers a surface of the semiconductor substrate and a surface of the first trench;
• performing a first doping process and a second doping process on the first doped polycrystalline silicon layer to form a second doped polycrystalline silicon layer on the surface of the semiconductor substrate and a portion of a bottom surface of the first trench, wherein the second doped polycrystalline silicon layer comprises a first doped sublayer with a second conduction type and a second doped sublayer with a first conduction type located on the first doped sublayer;
• performing a heat treatment process, so that the second doped polycrystalline silicon layer in the first trench extends toward side surfaces of the first trench;
• removing a portion of the second doped polycrystalline silicon layer to expose a portion of the bottom surface of the first trench;
• forming a body region at a bottom of the first trench and forming a source region located in the body region;
• performing a third doping process to form a drain region on the surface of the semiconductor substrate and a third doped sublayer with a second conduction type on a surface of the first doped polycrystalline silicon layer, wherein the second doped polycrystalline silicon layer, the first doped polycrystalline silicon layer, and the third doped sublayer on the side surfaces of the first trench serve as the junction field plate, and the first doped sublayer on the side surfaces of the first trench serves as a gate electrode;
• and
• forming a first lead-out structure electrically connected to the source region, a second lead-out structure electrically connected to the drain region and the third doped sublayer, and a third lead-out structure electrically connected to the gate electrode.