Split gate non-volatile memory cells, HV and logic devices with FINFET structures, and method of making same

A method of forming a memory device, comprising:

• forming a plurality of fins in an upper surface of a semiconductor substrate, wherein each of the fins extends upwardly and includes first and second side surfaces that oppose each other and that terminate in a top surface;
• and
• forming a memory cell on first and second fins of the plurality of fins, a high voltage (HV) device on a third fin of the plurality of fins, and a logic device on a fourth fin of the plurality of fins, by:
• forming a floating gate between the first and second fins;
• forming a control gate over and insulated from the floating gate;
• forming a layer of conductive material over the first fin, the second fin, the third fin and the fourth fin, wherein the layer of conductive material is polysilicon;
• selectively removing portions of the layer of conductive material, leaving:
• a word line gate as a first remaining portion of the layer of conductive material over the first and second fins,
• an erase gate as a second remaining portion of the layer of conductive material over the first and second fins, wherein the control gate is disposed between the word line gate and the erase gate,
• a HV gate as a third remaining portion of the layer of conductive material over the third fin, and
• a dummy gate as a fourth remaining portion of the layer of conductive material over the fourth fin;
• forming a source region in the first fin adjacent the erase gate;
• forming a first drain region in the first fin adjacent the word line gate;
• forming a second drain region in the first fin between the word line gate and the control gate, wherein a first channel region of the first fin extends along the top surface and the first and second side surfaces of the first fin from the source region of the first fin to the second drain region of the first fin, and wherein a second channel region of the first fin extends along the top surface and the first and second side surfaces of the first fin from the first drain region of the first fin to the second drain region of the first fin, wherein the floating gate is disposed adjacent to the second side surface of the first fin for controlling a conductivity of a portion of the first channel region extending along the second side surface of the first fin, and wherein the floating gate is not disposed adjacent to the first side surface of the first fin;
• forming a source region in the second fin adjacent the erase gate;
• forming a first drain region in the second fin adjacent the word line gate;
• forming a second drain region in the second fin between the word line gate and the control gate, wherein a first channel region of the second fin extends along the top surface and the first and second side surfaces of the second fin from the source region of the second fin to the second drain region of the second fin, and wherein a second channel region of the second fin extends along the top surface and the first and second side surfaces of the second fin from the first drain region of the second fin to the second drain region of the second fin, wherein the floating gate is disposed adjacent to the first side surface of the second fin for controlling a conductivity of a portion of the first channel region extending along the first side surface of the second fin, and wherein the floating gate is not disposed adjacent to the second side surface of the second fin;
• wherein the word line gate wraps around the first fin such that the word line gate extends along and is insulated from the top and opposing side surfaces of the first fin for controlling a conductivity of the second channel region of the first fin from the first drain region of the first fin to the second drain region of the first fin;
• wherein the word line gate wraps around the second fin such that the word line gate extends along and is insulated from the top and opposing side surfaces of the second fin for controlling a conductivity of the second channel region of the second fin from the first drain region of the second fin to the second drain region of the second fin;
• forming source and drain regions in the third fin adjacent the HV gate, wherein a channel region of the third fin extends along the top surface and the first and second side surfaces of the third fin from the source region of the third fin to the drain region of the third fin;
• forming source and drain regions in the fourth fin adjacent the dummy gate, wherein a channel region of the fourth fin extends along the top surface and the first and second side surfaces of the fourth fin from the source region of the fourth fin to the drain region of the fourth fin;
• and
• replacing the dummy gate with a logic gate formed of metal while maintaining the HV gate as the third remaining portion of the layer of conductive material.